Search - vhdl sdram

[VHDL-FPGA-Verilog] DDRSDRAM

Description: DDR SDRAM的veilog hdl程序，经过验证效果不错-DDR SDRAM' s veilog hdl procedures, good results verified
Platform: | Size: 475136 | Author: 寒心雪林 | Hits:

[VHDL-FPGA-Verilog] sdram_ctrl1

Description: FPGA读写SDRAM的VHDL程序，已经测试过-FPGA to read and write the VHDL procedures SDRAM have been tested
Platform: | Size: 5120 | Author: 钟灿武 | Hits:

[VHDL-FPGA-Verilog] altera_sdram

Description: SDRAM控制器的VHDL代码在FGPA中的综合与实现-SDRAM controller VHDL code FGPA and implementation of integrated
Platform: | Size: 2383872 | Author: Mr Yang | Hits:

Description: 使用xilinx virtex4芯片，设计环境为EDK，其中包含uart,片外sram操作，flash操作，DDR SDRAM操作，MAC自发自收，audio，video等试验-Xilinx virtex4 use chip design environment for the EDK, which contains the uart, chip sram operation, flash operation, DDR SDRAM operation, MAC spontaneous self-admission, audio, video and other tests
Platform: | Size: 22821888 | Author: 肖姗姗 | Hits:

[Other] Micron_DDR

Description: DDR2 SDRAM 颗粒初始化以及读写操作时序-Particles as well as the DDR2 SDRAM initialization timing to read and write operations
Platform: | Size: 432128 | Author: robert.wang | Hits:

[Other] xilinx_sdcontroller

Description: xilinx公司的sdram控制器代码及说明文件-sdram controller of xilinx, codes and notes
Platform: | Size: 340992 | Author: 孙磊 | Hits:

[Other] Sdram_Control_4Port

Description: SDRAM控制器HDL实现，sdram为美光公司的-sdram controller
Platform: | Size: 3072 | Author: paladin | Hits:

[VHDL-FPGA-Verilog] SDRAMcontrollor

Description: SDRAM控制器，以下是我用VHDL编写SDRAM Controller的全部资料。文档提供的SDRAM控制器能工作在125MHz，我在实际工程中用到了120MHz，但没有再往上做测试了-SDRAM controller, the following is my SDRAM Controller using VHDL to prepare all the information. Documentation provided by SDRAM controller can work in the 125MHz, I used in the actual works of 120MHz, but did not do test in 125MHz or more
Platform: | Size: 6203392 | Author: 何宗奎 | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: verilog 128位突发4. sdr fpga控制器-verilog 128 bit unexpected 4. sdr fpga controller
Platform: | Size: 119808 | Author: pudnrtest | Hits:

[VHDL-FPGA-Verilog] webCam-FPGA

Description: 使用Verilog控制美光CMOS图像处理器，并转存到SDRAM中。使用FPGA为QL的带fuse系列-Control the use of Verilog Micron CMOS image processor and SDRAM in转存到. FPGA for use with QL series fuse
Platform: | Size: 36864 | Author: NOOW | Hits:

[VHDL-FPGA-Verilog] WRCTRL

Description: this VHDL Program get a 64 bit data and send it to a SDRAM-controller block to write into SDRAM and then get a 64bits data from SDR-block
Platform: | Size: 2048 | Author: Taher Aghazadeh | Hits:

[VHDL-FPGA-Verilog] Xil3SD1800A_MIG_simplifiedUI_vlog_v92

Description: verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
Platform: | Size: 908288 | Author: ma yirong | Hits:

[VHDL-FPGA-Verilog] CAST_sdr_sdram_ctrl-xact

Description: Single Data Rate Mobile SDRAM Controller Core with AHB Interface
Platform: | Size: 733184 | Author: gosha | Hits:

[VHDL-FPGA-Verilog] cameralink

Description: 由于目前基于CameraLink接口的各种相机都不能直接显示，因此本文基于Xilinx公司的Spartan 3系列FPGAXC3S1000-6FG456I设计了一套实时显示系统，该系统可以在不通过系统机的情况下，完成对相机CameraLink信号的接收、缓存、读取并显示系统采用两片SDRAM作为帧缓存，将输入的CameraLink信号转换成帧频为75Hz，分辨率为1 024×768的XGA格式信号，并采用ADV7123JST芯片实现数模转换，将芯片输出的信号送到VGA接口，通过VGA显示器显示出来-As the CameraLink interface is currently based on a variety of cameras can not directly display, this article based on Xilinx' s Spartan 3 series FPGAXC3S1000-6FG456I designed a set of real-time display system, the system can be achieved without machine case through the system to complete the CameraLink cameras signal reception, cache, read and display systems use two SDRAM frame buffer as the input signals into the CameraLink frame rate of 75Hz, a resolution of 1 024 × 768 for XGA format signal, and using ADV7123JST chip digital-analog conversion, the chip output signal to the VGA port, through the VGA display monitor
Platform: | Size: 13312 | Author: lilei | Hits:

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[VHDL-FPGA-Verilog] DDRSDRAM

[VHDL-FPGA-Verilog] sdram_ctrl1

[VHDL-FPGA-Verilog] altera_sdram

[VHDL-FPGA-Verilog] 03.EDK8.2

[Other] Micron_DDR

[Other] xilinx_sdcontroller

[Other] Sdram_Control_4Port

[VHDL-FPGA-Verilog] SDRAMcontrollor

[VHDL-FPGA-Verilog] SDRAM

[VHDL-FPGA-Verilog] webCam-FPGA

[VHDL-FPGA-Verilog] WRCTRL

[VHDL-FPGA-Verilog] Xil3SD1800A_MIG_simplifiedUI_vlog_v92

[VHDL-FPGA-Verilog] CAST_sdr_sdram_ctrl-xact

[VHDL-FPGA-Verilog] cameralink

[VHDL-FPGA-Verilog] ddr_verilog_xilinx

[VHDL-FPGA-Verilog] DE2_LCM_CCD

[VHDL-FPGA-Verilog] ddr_sdram_controller_vhdl

[VHDL-FPGA-Verilog] HY57V641620HG.vp

[Other Embeded program] SDRAM_design_source

[VHDL-FPGA-Verilog] mt48lc4m32b2.v

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